1. Field
An embodiment of the present disclosure relates to a memory system and an operating method thereof, and more particularly, to a wake-up operation of a SDR/DDR combined memory system.
2. Description of the Related Art
A synchronous memory system may operate in a single data rate (SDR) mode in which one-bit data is input/output per one data input/output pin during one clock cycle, or operate in a double data rate (DDR) mode in which two-bit data is input/output per one data input/output pin during one clock cycle. The synchronous memory system of the SDR mode has excellent reliability, and the synchronous memory system of the DDR mode has fast operation speed.
Accordingly, SDR/DDR combined memory systems having advantages of the SDR mode and the DDR mode are increasingly being used.
The SDR/DDR combined memory system may operate in the SDR mode or the DDR mode. In general, a booting operation of the memory system is performed in the SDR mode to ensure the reliability of the memory system, and general operations of the memory system after completion of the booting operation are performed in the DDR mode.
Since the SDR/DDR combined memory system operates in the SDR mode or the DDR mode, the mode of the memory system is reset during a wake-up operation for re-operation after power is off.
The memory system may include a memory controller which outputs control signals in response to a command received from a host, and a memory device which performs a program, read, or erase operation in response to the control signals. Each of the memory controller and the memory device is set to the SDR mode or the DDR mode according to an operation thereof. During an operation of the SDR mode, both the memory controller and the memory device are set to the SDR mode. During an operation of the DDR mode, both the memory controller and the memory device are set to the DDR mode.
In general, during the wake-up operation, the memory controller is initialized to the SDR mode, and the memory device is also initialized to the SDR mode regardless of its previous mode before the wake-up operation. Then, the modes of the memory controller and the memory device are reset according to its previous mode before the wake-up operation. Therefore, as the time required to initialize the memory controller and the memory device increases, the total operating time of the memory system may increase.